10 #include "RF24_config.h" 15 void RF24::csn(
bool mode)
18 #if defined (RF24_TINY) 19 if (ce_pin != csn_pin) {
20 digitalWrite(csn_pin,mode);
25 delayMicroseconds(100);
29 delayMicroseconds(11);
35 #elif defined(ARDUINO) && !defined (RF24_SPI_TRANSACTIONS) 41 #if !defined (SOFTSPI) 42 _SPI.setBitOrder(MSBFIRST);
43 _SPI.setDataMode(SPI_MODE0);
44 _SPI.setClockDivider(SPI_CLOCK_DIV2);
46 #elif defined (RF24_RPi) 48 _SPI.chipSelect(csn_pin);
51 #if !defined (RF24_LINUX) 52 digitalWrite(csn_pin,mode);
60 void RF24::ce(
bool level)
63 if (ce_pin != csn_pin) digitalWrite(ce_pin,level);
69 #if defined (RF24_SPI_TRANSACTIONS) 70 _SPI.beginTransaction(SPISettings(RF24_SPI_SPEED, MSBFIRST, SPI_MODE0));
77 inline void RF24::endTransaction() {
79 #if defined (RF24_SPI_TRANSACTIONS) 80 _SPI.endTransaction();
86 uint8_t RF24::read_register(uint8_t reg, uint8_t* buf, uint8_t len)
90 #if defined (RF24_LINUX) 92 uint8_t * prx = spi_rxbuff;
93 uint8_t * ptx = spi_txbuff;
94 uint8_t size = len + 1;
96 *ptx++ = ( R_REGISTER | ( REGISTER_MASK & reg ) );
98 while (len--){ *ptx++ = NOP; }
100 _SPI.transfernb( (
char *) spi_txbuff, (
char *) spi_rxbuff, size);
105 while ( --size ){ *buf++ = *prx++; }
111 status = _SPI.transfer( R_REGISTER | ( REGISTER_MASK & reg ) );
113 *buf++ = _SPI.transfer(0xff);
124 uint8_t RF24::read_register(uint8_t reg)
128 #if defined (RF24_LINUX) 132 uint8_t * prx = spi_rxbuff;
133 uint8_t * ptx = spi_txbuff;
134 *ptx++ = ( R_REGISTER | ( REGISTER_MASK & reg ) );
137 _SPI.transfernb( (
char *) spi_txbuff, (
char *) spi_rxbuff, 2);
144 _SPI.transfer( R_REGISTER | ( REGISTER_MASK & reg ) );
145 result = _SPI.transfer(0xff);
155 uint8_t RF24::write_register(uint8_t reg,
const uint8_t* buf, uint8_t len)
159 #if defined (RF24_LINUX) 161 uint8_t * prx = spi_rxbuff;
162 uint8_t * ptx = spi_txbuff;
163 uint8_t size = len + 1;
165 *ptx++ = ( W_REGISTER | ( REGISTER_MASK & reg ) );
169 _SPI.transfernb( (
char *) spi_txbuff, (
char *) spi_rxbuff, size);
175 status = _SPI.transfer( W_REGISTER | ( REGISTER_MASK & reg ) );
177 _SPI.transfer(*buf++);
187 uint8_t RF24::write_register(uint8_t reg, uint8_t value)
191 IF_SERIAL_DEBUG(printf_P(PSTR(
"write_register(%02x,%02x)\r\n"),reg,value));
193 #if defined (RF24_LINUX) 195 uint8_t * prx = spi_rxbuff;
196 uint8_t * ptx = spi_txbuff;
197 *ptx++ = ( W_REGISTER | ( REGISTER_MASK & reg ) );
200 _SPI.transfernb( (
char *) spi_txbuff, (
char *) spi_rxbuff, 2);
206 status = _SPI.transfer( W_REGISTER | ( REGISTER_MASK & reg ) );
207 _SPI.transfer(value);
217 uint8_t RF24::write_payload(
const void* buf, uint8_t data_len,
const uint8_t writeType)
220 const uint8_t* current =
reinterpret_cast<const uint8_t*
>(buf);
222 data_len = rf24_min(data_len, payload_size);
223 uint8_t blank_len = dynamic_payloads_enabled ? 0 : payload_size - data_len;
226 IF_SERIAL_DEBUG( printf(
"[Writing %u bytes %u blanks]\n",data_len,blank_len); );
228 #if defined (RF24_LINUX) 230 uint8_t * prx = spi_rxbuff;
231 uint8_t * ptx = spi_txbuff;
233 size = data_len + blank_len + 1 ;
238 while ( blank_len-- )
241 _SPI.transfernb( (
char *) spi_txbuff, (
char *) spi_rxbuff, size);
248 status = _SPI.transfer( writeType );
249 while ( data_len-- ) {
250 _SPI.transfer(*current++);
252 while ( blank_len-- ) {
264 uint8_t RF24::read_payload(
void* buf, uint8_t data_len)
267 uint8_t* current =
reinterpret_cast<uint8_t*
>(buf);
269 if(data_len > payload_size) data_len = payload_size;
270 uint8_t blank_len = dynamic_payloads_enabled ? 0 : payload_size - data_len;
274 IF_SERIAL_DEBUG( printf(
"[Reading %u bytes %u blanks]\n",data_len,blank_len); );
276 #if defined (RF24_LINUX) 278 uint8_t * prx = spi_rxbuff;
279 uint8_t * ptx = spi_txbuff;
281 size = data_len + blank_len + 1;
283 *ptx++ = R_RX_PAYLOAD;
287 size = data_len + blank_len + 1;
289 _SPI.transfernb( (
char *) spi_txbuff, (
char *) spi_rxbuff, size);
301 status = _SPI.transfer( R_RX_PAYLOAD );
302 while ( data_len-- ) {
303 *current++ = _SPI.transfer(0xFF);
305 while ( blank_len-- ) {
317 uint8_t RF24::flush_rx(
void)
319 return spiTrans( FLUSH_RX );
326 return spiTrans( FLUSH_TX );
331 uint8_t RF24::spiTrans(uint8_t cmd){
336 status = _SPI.transfer( cmd );
344 uint8_t RF24::get_status(
void)
346 return spiTrans(NOP);
350 #if !defined (MINIMAL) 351 void RF24::print_status(uint8_t status)
353 printf_P(PSTR(
"STATUS\t\t = 0x%02x RX_DR=%x TX_DS=%x MAX_RT=%x RX_P_NO=%x TX_FULL=%x\r\n"),
355 (status & _BV(RX_DR))?1:0,
356 (status & _BV(TX_DS))?1:0,
357 (status & _BV(MAX_RT))?1:0,
358 ((status >> RX_P_NO) & 0b111),
359 (status & _BV(TX_FULL))?1:0
365 void RF24::print_observe_tx(uint8_t value)
367 printf_P(PSTR(
"OBSERVE_TX=%02x: POLS_CNT=%x ARC_CNT=%x\r\n"),
369 (value >> PLOS_CNT) & 0b1111,
370 (value >> ARC_CNT) & 0b1111
376 void RF24::print_byte_register(
const char* name, uint8_t reg, uint8_t qty)
380 #if defined (RF24_LINUX) 381 printf(
"%s\t =", name);
383 printf_P(PSTR(PRIPSTR
"\t ="),name);
386 printf_P(PSTR(
" 0x%02x"),read_register(reg++));
387 printf_P(PSTR(
"\r\n"));
392 void RF24::print_address_register(
const char* name, uint8_t reg, uint8_t qty)
395 #if defined (RF24_LINUX) 396 printf(
"%s\t =",name);
398 printf_P(PSTR(PRIPSTR
"\t ="),name);
402 uint8_t buffer[addr_width];
403 read_register(reg++,buffer,
sizeof buffer);
405 printf_P(PSTR(
" 0x"));
406 uint8_t* bufptr = buffer +
sizeof buffer;
407 while( --bufptr >= buffer )
408 printf_P(PSTR(
"%02x"),*bufptr);
411 printf_P(PSTR(
"\r\n"));
417 ce_pin(_cepin), csn_pin(_cspin), p_variant(false),
418 payload_size(32), dynamic_payloads_enabled(false), addr_width(5)
420 pipe0_reading_address[0]=0;
425 #if defined (RF24_LINUX) && !defined (MRAA)//RPi constructor 426 RF24::RF24(uint8_t _cepin, uint8_t _cspin, uint32_t _spi_speed):
427 ce_pin(_cepin),csn_pin(_cspin),spi_speed(_spi_speed),p_variant(
false), payload_size(32), dynamic_payloads_enabled(
false),addr_width(5)
429 pipe0_reading_address[0]=0;
437 const uint8_t max_channel = 125;
438 write_register(RF_CH,rf24_min(channel,max_channel));
444 return read_register(RF_CH);
450 payload_size = rf24_min(size,32);
462 #if !defined (MINIMAL) 464 static const char rf24_datarate_e_str_0[] PROGMEM =
"1MBPS";
465 static const char rf24_datarate_e_str_1[] PROGMEM =
"2MBPS";
466 static const char rf24_datarate_e_str_2[] PROGMEM =
"250KBPS";
467 static const char *
const rf24_datarate_e_str_P[] PROGMEM = {
468 rf24_datarate_e_str_0,
469 rf24_datarate_e_str_1,
470 rf24_datarate_e_str_2,
472 static const char rf24_model_e_str_0[] PROGMEM =
"nRF24L01";
473 static const char rf24_model_e_str_1[] PROGMEM =
"nRF24L01+";
474 static const char *
const rf24_model_e_str_P[] PROGMEM = {
478 static const char rf24_crclength_e_str_0[] PROGMEM =
"Disabled";
479 static const char rf24_crclength_e_str_1[] PROGMEM =
"8 bits";
480 static const char rf24_crclength_e_str_2[] PROGMEM =
"16 bits" ;
481 static const char *
const rf24_crclength_e_str_P[] PROGMEM = {
482 rf24_crclength_e_str_0,
483 rf24_crclength_e_str_1,
484 rf24_crclength_e_str_2,
486 static const char rf24_pa_dbm_e_str_0[] PROGMEM =
"PA_MIN";
487 static const char rf24_pa_dbm_e_str_1[] PROGMEM =
"PA_LOW";
488 static const char rf24_pa_dbm_e_str_2[] PROGMEM =
"PA_HIGH";
489 static const char rf24_pa_dbm_e_str_3[] PROGMEM =
"PA_MAX";
490 static const char *
const rf24_pa_dbm_e_str_P[] PROGMEM = {
497 #if defined (RF24_LINUX) 498 static const char rf24_csn_e_str_0[] =
"CE0 (PI Hardware Driven)";
499 static const char rf24_csn_e_str_1[] =
"CE1 (PI Hardware Driven)";
500 static const char rf24_csn_e_str_2[] =
"CE2 (PI Hardware Driven)";
501 static const char rf24_csn_e_str_3[] =
"Custom GPIO Software Driven";
502 static const char *
const rf24_csn_e_str_P[] = {
513 #if defined (RF24_RPi) 514 printf(
"================ SPI Configuration ================\n" );
515 if (csn_pin < BCM2835_SPI_CS_NONE ){
516 printf(
"CSN Pin \t = %s\n",rf24_csn_e_str_P[csn_pin]);
518 printf(
"CSN Pin \t = Custom GPIO%d%s\n", csn_pin,
519 csn_pin==RPI_V2_GPIO_P1_26 ?
" (CE1) Software Driven" :
"" );
521 printf(
"CE Pin \t = Custom GPIO%d\n", ce_pin );
522 printf(
"Clock Speed\t = " );
525 case BCM2835_SPI_SPEED_64MHZ : printf(
"64 Mhz"); break ;
526 case BCM2835_SPI_SPEED_32MHZ : printf(
"32 Mhz"); break ;
527 case BCM2835_SPI_SPEED_16MHZ : printf(
"16 Mhz"); break ;
528 case BCM2835_SPI_SPEED_8MHZ : printf(
"8 Mhz"); break ;
529 case BCM2835_SPI_SPEED_4MHZ : printf(
"4 Mhz"); break ;
530 case BCM2835_SPI_SPEED_2MHZ : printf(
"2 Mhz"); break ;
531 case BCM2835_SPI_SPEED_1MHZ : printf(
"1 Mhz"); break ;
532 case BCM2835_SPI_SPEED_512KHZ: printf(
"512 KHz"); break ;
533 case BCM2835_SPI_SPEED_256KHZ: printf(
"256 KHz"); break ;
534 case BCM2835_SPI_SPEED_128KHZ: printf(
"128 KHz"); break ;
535 case BCM2835_SPI_SPEED_64KHZ : printf(
"64 KHz"); break ;
536 case BCM2835_SPI_SPEED_32KHZ : printf(
"32 KHz"); break ;
537 case BCM2835_SPI_SPEED_16KHZ : printf(
"16 KHz"); break ;
538 case BCM2835_SPI_SPEED_8KHZ : printf(
"8 KHz"); break ;
539 default : printf(
"8 Mhz"); break ;
541 printf(
"\n================ NRF Configuration ================\n");
545 print_status(get_status());
547 print_address_register(PSTR(
"RX_ADDR_P0-1"),RX_ADDR_P0,2);
548 print_byte_register(PSTR(
"RX_ADDR_P2-5"),RX_ADDR_P2,4);
549 print_address_register(PSTR(
"TX_ADDR\t"),TX_ADDR);
551 print_byte_register(PSTR(
"RX_PW_P0-6"),RX_PW_P0,6);
552 print_byte_register(PSTR(
"EN_AA\t"),EN_AA);
553 print_byte_register(PSTR(
"EN_RXADDR"),EN_RXADDR);
554 print_byte_register(PSTR(
"RF_CH\t"),RF_CH);
555 print_byte_register(PSTR(
"RF_SETUP"),RF_SETUP);
556 print_byte_register(PSTR(
"CONFIG\t"),CONFIG);
557 print_byte_register(PSTR(
"DYNPD/FEATURE"),DYNPD,2);
559 printf_P(PSTR(
"Data Rate\t = " PRIPSTR
"\r\n"),pgm_read_word(&rf24_datarate_e_str_P[
getDataRate()]));
560 printf_P(PSTR(
"Model\t\t = " PRIPSTR
"\r\n"),pgm_read_word(&rf24_model_e_str_P[
isPVariant()]));
561 printf_P(PSTR(
"CRC Length\t = " PRIPSTR
"\r\n"),pgm_read_word(&rf24_crclength_e_str_P[
getCRCLength()]));
562 printf_P(PSTR(
"PA Power\t = " PRIPSTR
"\r\n"), pgm_read_word(&rf24_pa_dbm_e_str_P[
getPALevel()]));
574 #if defined (RF24_LINUX) 580 gpio.begin(ce_pin,csn_pin);
588 case 8: csn_pin = 0;
break;
589 case 7: csn_pin = 1;
break;
590 default: csn_pin = 0;
break;
595 pinMode(ce_pin,OUTPUT);
600 #elif defined(LITTLEWIRE) 601 pinMode(csn_pin,OUTPUT);
606 if (ce_pin != csn_pin) pinMode(ce_pin,OUTPUT);
608 #if ! defined(LITTLEWIRE) 609 if (ce_pin != csn_pin)
611 pinMode(csn_pin,OUTPUT);
616 #if defined (__ARDUINO_X86__) 630 write_register( CONFIG, 0b00001100 ) ;
646 setup = read_register(RF_SETUP);
661 write_register(FEATURE,0 );
662 write_register(DYNPD,0);
666 write_register(NRF_STATUS,_BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) );
681 write_register(CONFIG, ( read_register(CONFIG) ) & ~_BV(PRIM_RX) );
684 return ( setup != 0 && setup != 0xff );
691 #if !defined (RF24_TINY) && ! defined(LITTLEWIRE) 694 write_register(CONFIG, read_register(CONFIG) | _BV(PRIM_RX));
695 write_register(NRF_STATUS, _BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) );
698 if (pipe0_reading_address[0] > 0){
699 write_register(RX_ADDR_P0, pipe0_reading_address, addr_width);
706 if(read_register(FEATURE) & _BV(EN_ACK_PAY)){
715 static const uint8_t child_pipe_enable[] PROGMEM =
717 ERX_P0, ERX_P1, ERX_P2, ERX_P3, ERX_P4, ERX_P5
724 delayMicroseconds(txRxDelay);
726 if(read_register(FEATURE) & _BV(EN_ACK_PAY)){
727 delayMicroseconds(txRxDelay);
731 write_register(CONFIG, ( read_register(CONFIG) ) & ~_BV(PRIM_RX) );
733 #if defined (RF24_TINY) || defined (LITTLEWIRE) 735 if (ce_pin == csn_pin) {
740 write_register(EN_RXADDR,read_register(EN_RXADDR) | _BV(pgm_read_byte(&child_pipe_enable[0])));
751 write_register(CONFIG,read_register(CONFIG) & ~_BV(PWR_UP));
759 uint8_t cfg = read_register(CONFIG);
762 if (!(cfg & _BV(PWR_UP))){
763 write_register(CONFIG,read_register(CONFIG) | _BV(PWR_UP));
773 #if defined (FAILURE_HANDLING) || defined (RF24_LINUX) 774 void RF24::errNotify(){
775 #if defined (SERIAL_DEBUG) || defined (RF24_LINUX) 776 printf_P(PSTR(
"RF24 HARDWARE FAIL: Radio not responding, verify pin connections, wiring, etc.\r\n"));
778 #if defined (FAILURE_HANDLING) 788 bool RF24::write(
const void* buf, uint8_t len,
const bool multicast )
794 #if defined (FAILURE_HANDLING) || defined (RF24_LINUX) 795 uint32_t timer = millis();
798 while( ! ( get_status() & ( _BV(TX_DS) | _BV(MAX_RT) ))) {
799 #if defined (FAILURE_HANDLING) || defined (RF24_LINUX) 800 if(millis() - timer > 85){
802 #if defined (FAILURE_HANDLING) 813 uint8_t status = write_register(NRF_STATUS,_BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) );
816 if( status & _BV(MAX_RT)){
825 return write(buf,len,0);
837 uint32_t timer = millis();
839 while( ( get_status() & ( _BV(TX_FULL) ))) {
841 if( get_status() & _BV(MAX_RT)){
843 if(millis() - timer > timeout){
return 0; }
845 #if defined (FAILURE_HANDLING) || defined (RF24_LINUX) 846 if(millis() - timer > (timeout+85) ){
848 #if defined (FAILURE_HANDLING) 865 write_register(NRF_STATUS,_BV(MAX_RT) );
866 spiTrans( REUSE_TX_PL );
880 #if defined (FAILURE_HANDLING) || defined (RF24_LINUX) 881 uint32_t timer = millis();
884 while( ( get_status() & ( _BV(TX_FULL) ))) {
886 if( get_status() & _BV(MAX_RT)){
888 write_register(NRF_STATUS,_BV(MAX_RT) );
892 #if defined (FAILURE_HANDLING) || defined (RF24_LINUX) 893 if(millis() - timer > 85 ){
895 #if defined (FAILURE_HANDLING) 921 write_payload( buf, len,multicast ? W_TX_PAYLOAD_NO_ACK : W_TX_PAYLOAD ) ;
937 write_payload( buf, len,multicast? W_TX_PAYLOAD_NO_ACK : W_TX_PAYLOAD ) ;
939 #if defined(CORE_TEENSY) || !defined(ARDUINO) || defined (RF24_BBB) || defined (RF24_DUE) 940 delayMicroseconds(10);
950 return read_register(FIFO_STATUS) & _BV(RX_FULL);
956 #if defined (FAILURE_HANDLING) || defined (RF24_LINUX) 957 uint32_t timeout = millis();
959 while( ! (read_register(FIFO_STATUS) & _BV(TX_EMPTY)) ){
960 if( get_status() & _BV(MAX_RT)){
961 write_register(NRF_STATUS,_BV(MAX_RT) );
966 #if defined (FAILURE_HANDLING) || defined (RF24_LINUX) 967 if( millis() - timeout > 85){
969 #if defined (FAILURE_HANDLING) 988 uint32_t start = millis();
990 while( ! (read_register(FIFO_STATUS) & _BV(TX_EMPTY)) ){
991 if( get_status() & _BV(MAX_RT)){
992 write_register(NRF_STATUS,_BV(MAX_RT) );
995 if(millis() - start >= timeout){
999 #if defined (FAILURE_HANDLING) || defined (RF24_LINUX) 1000 if( millis() - start > (timeout+85)){
1002 #if defined (FAILURE_HANDLING) 1019 uint8_t config = read_register(CONFIG);
1021 config &= ~(1 << MASK_MAX_RT | 1 << MASK_TX_DS | 1 << MASK_RX_DR);
1023 config |= fail << MASK_MAX_RT | tx << MASK_TX_DS | rx << MASK_RX_DR;
1024 write_register(CONFIG, config);
1033 #if defined (RF24_LINUX) 1034 spi_txbuff[0] = R_RX_PL_WID;
1035 spi_rxbuff[1] = 0xff;
1037 _SPI.transfernb( (
char *) spi_txbuff, (
char *) spi_rxbuff, 2);
1038 result = spi_rxbuff[1];
1042 _SPI.transfer( R_RX_PL_WID );
1043 result = _SPI.transfer(0xff);
1047 if(result > 32) { flush_rx(); delay(2);
return 0; }
1062 if (!( read_register(FIFO_STATUS) & _BV(RX_EMPTY) )){
1066 uint8_t status = get_status();
1067 *pipe_num = ( status >> RX_P_NO ) & 0b111;
1083 read_payload( buf, len );
1086 write_register(NRF_STATUS,_BV(RX_DR) | _BV(MAX_RT) | _BV(TX_DS) );
1096 uint8_t status = write_register(NRF_STATUS,_BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) );
1099 tx_ok = status & _BV(TX_DS);
1100 tx_fail = status & _BV(MAX_RT);
1101 rx_ready = status & _BV(RX_DR);
1111 write_register(RX_ADDR_P0, reinterpret_cast<uint8_t*>(&value), addr_width);
1112 write_register(TX_ADDR, reinterpret_cast<uint8_t*>(&value), addr_width);
1117 write_register(RX_PW_P0,payload_size);
1126 write_register(RX_ADDR_P0,address, addr_width);
1127 write_register(TX_ADDR, address, addr_width);
1131 write_register(RX_PW_P0,payload_size);
1135 static const uint8_t child_pipe[] PROGMEM =
1137 RX_ADDR_P0, RX_ADDR_P1, RX_ADDR_P2, RX_ADDR_P3, RX_ADDR_P4, RX_ADDR_P5
1139 static const uint8_t child_payload_size[] PROGMEM =
1141 RX_PW_P0, RX_PW_P1, RX_PW_P2, RX_PW_P3, RX_PW_P4, RX_PW_P5
1151 memcpy(pipe0_reading_address,&address,addr_width);
1158 write_register(pgm_read_byte(&child_pipe[child]), reinterpret_cast<const uint8_t*>(&address), addr_width);
1160 write_register(pgm_read_byte(&child_pipe[child]), reinterpret_cast<const uint8_t*>(&address), 1);
1162 write_register(pgm_read_byte(&child_payload_size[child]),payload_size);
1167 write_register(EN_RXADDR,read_register(EN_RXADDR) | _BV(pgm_read_byte(&child_pipe_enable[child])));
1175 write_register(SETUP_AW,a_width%4);
1176 addr_width = (a_width%4) + 2;
1189 memcpy(pipe0_reading_address,address,addr_width);
1195 write_register(pgm_read_byte(&child_pipe[child]), address, addr_width);
1197 write_register(pgm_read_byte(&child_pipe[child]), address, 1);
1199 write_register(pgm_read_byte(&child_payload_size[child]),payload_size);
1204 write_register(EN_RXADDR,read_register(EN_RXADDR) | _BV(pgm_read_byte(&child_pipe_enable[child])));
1213 write_register(EN_RXADDR,read_register(EN_RXADDR) & ~_BV(pgm_read_byte(&child_pipe_enable[pipe])));
1218 void RF24::toggle_features(
void)
1221 _SPI.transfer( ACTIVATE );
1222 _SPI.transfer( 0x73 );
1233 write_register(FEATURE,read_register(FEATURE) | _BV(EN_DPL) );
1236 IF_SERIAL_DEBUG(printf(
"FEATURE=%i\r\n",read_register(FEATURE)));
1242 write_register(DYNPD,read_register(DYNPD) | _BV(DPL_P5) | _BV(DPL_P4) | _BV(DPL_P3) | _BV(DPL_P2) | _BV(DPL_P1) | _BV(DPL_P0));
1244 dynamic_payloads_enabled =
true;
1256 write_register(FEATURE,read_register(FEATURE) | _BV(EN_ACK_PAY) | _BV(EN_DPL) );
1258 IF_SERIAL_DEBUG(printf(
"FEATURE=%i\r\n",read_register(FEATURE)));
1264 write_register(DYNPD,read_register(DYNPD) | _BV(DPL_P1) | _BV(DPL_P0));
1265 dynamic_payloads_enabled =
true;
1275 write_register(FEATURE,read_register(FEATURE) | _BV(EN_DYN_ACK) );
1277 IF_SERIAL_DEBUG(printf(
"FEATURE=%i\r\n",read_register(FEATURE)));
1286 const uint8_t* current =
reinterpret_cast<const uint8_t*
>(buf);
1288 uint8_t data_len = rf24_min(len,32);
1290 #if defined (RF24_LINUX) 1292 uint8_t * ptx = spi_txbuff;
1293 uint8_t size = data_len + 1 ;
1294 *ptx++ = W_ACK_PAYLOAD | ( pipe & 0b111 );
1295 while ( data_len-- ){
1296 *ptx++ = *current++;
1299 _SPI.transfern( (
char *) spi_txbuff, size);
1303 _SPI.transfer(W_ACK_PAYLOAD | ( pipe & 0b111 ) );
1305 while ( data_len-- )
1306 _SPI.transfer(*current++);
1317 return ! (read_register(FIFO_STATUS) & _BV(RX_EMPTY));
1332 write_register(EN_AA, 0b111111);
1334 write_register(EN_AA, 0);
1343 uint8_t en_aa = read_register( EN_AA ) ;
1346 en_aa |= _BV(pipe) ;
1350 en_aa &= ~_BV(pipe) ;
1352 write_register( EN_AA, en_aa ) ;
1360 return ( read_register(CD) & 1 );
1367 return ( read_register(RPD) & 1 ) ;
1375 uint8_t setup = read_register(RF_SETUP) & 0b11111000;
1378 level = (RF24_PA_MAX << 1) + 1;
1380 level = (level << 1) + 1;
1384 write_register( RF_SETUP, setup |= level ) ;
1392 return (read_register(RF_SETUP) & (_BV(RF_PWR_LOW) | _BV(RF_PWR_HIGH))) >> 1 ;
1399 bool result =
false;
1400 uint8_t setup = read_register(RF_SETUP) ;
1403 setup &= ~(_BV(RF_DR_LOW) | _BV(RF_DR_HIGH)) ;
1405 #if defined(__arm__) || defined (RF24_LINUX) || defined (__ARDUINO_X86__) 1407 #else //16Mhz Arduino 1410 if( speed == RF24_250KBPS )
1414 setup |= _BV( RF_DR_LOW ) ;
1415 #if defined(__arm__) || defined (RF24_LINUX) || defined (__ARDUINO_X86__) 1417 #else //16Mhz Arduino 1425 if ( speed == RF24_2MBPS )
1427 setup |= _BV(RF_DR_HIGH);
1428 #if defined(__arm__) || defined (RF24_LINUX) || defined (__ARDUINO_X86__) 1430 #else //16Mhz Arduino 1435 write_register(RF_SETUP,setup);
1438 if ( read_register(RF_SETUP) == setup )
1450 uint8_t dr = read_register(RF_SETUP) & (_BV(RF_DR_LOW) | _BV(RF_DR_HIGH));
1454 if ( dr == _BV(RF_DR_LOW) )
1457 result = RF24_250KBPS ;
1459 else if ( dr == _BV(RF_DR_HIGH) )
1462 result = RF24_2MBPS ;
1467 result = RF24_1MBPS ;
1476 uint8_t config = read_register(CONFIG) & ~( _BV(CRCO) | _BV(EN_CRC)) ;
1479 if ( length == RF24_CRC_DISABLED )
1483 else if ( length == RF24_CRC_8 )
1485 config |= _BV(EN_CRC);
1489 config |= _BV(EN_CRC);
1490 config |= _BV( CRCO );
1492 write_register( CONFIG, config ) ;
1501 uint8_t config = read_register(CONFIG) & ( _BV(CRCO) | _BV(EN_CRC)) ;
1502 uint8_t AA = read_register(EN_AA);
1504 if ( config & _BV(EN_CRC ) || AA)
1506 if ( config & _BV(CRCO) )
1507 result = RF24_CRC_16;
1509 result = RF24_CRC_8;
1519 uint8_t disable = read_register(CONFIG) & ~_BV(EN_CRC) ;
1520 write_register( CONFIG, disable ) ;
1526 write_register(SETUP_RETR,(delay&0xf)<<ARD | (count&0xf)<<ARC);
1532 #if defined(__AVR_ATtiny25__) || defined(__AVR_ATtiny45__) || defined(__AVR_ATtiny85__) 1534 # define DI 0 // D0, pin 5 Data In 1535 # define DO 1 // D1, pin 6 Data Out (this is *not* MOSI) 1536 # define USCK 2 // D2, pin 7 Universal Serial Interface clock 1537 # define SS 3 // D3, pin 2 Slave Select 1538 #elif defined(__AVR_ATtiny24__) || defined(__AVR_ATtiny44__) || defined(__AVR_ATtiny84__) 1541 # define DI 4 // PA6 1542 # define DO 5 // PA5 1543 # define USCK 6 // PA4 1544 # define SS 3 // PA7 1545 #elif defined(__AVR_ATtiny2313__) || defined(__AVR_ATtiny4313__) 1548 # define DI 14 // PB5 1549 # define DO 15 // PB6 1550 # define USCK 16 // PB7 1551 # define SS 13 // PB4 1554 #if defined(RF24_TINY) 1556 void SPIClass::begin() {
1558 pinMode(USCK, OUTPUT);
1559 pinMode(DO, OUTPUT);
1561 USICR = _BV(USIWM0);
1565 byte SPIClass::transfer(byte b) {
1568 USISR = _BV(USIOIF);
1570 USICR = _BV(USIWM0) | _BV(USICS1) | _BV(USICLK) | _BV(USITC);
1571 while ((USISR & _BV(USIOIF)) == 0);
1576 void SPIClass::end() {}
1577 void SPIClass::setDataMode(uint8_t mode){}
1578 void SPIClass::setBitOrder(uint8_t bitOrder){}
1579 void SPIClass::setClockDivider(uint8_t rate){}
void setAutoAck(bool enable)
bool isAckPayloadAvailable(void)
void closeReadingPipe(uint8_t pipe)
void startWrite(const void *buf, uint8_t len, const bool multicast)
void enableAckPayload(void)
void maskIRQ(bool tx_ok, bool tx_fail, bool rx_ready)
uint8_t getPayloadSize(void)
void setChannel(uint8_t channel)
void setRetries(uint8_t delay, uint8_t count)
bool write(const void *buf, uint8_t len)
void startListening(void)
bool writeBlocking(const void *buf, uint8_t len, uint32_t timeout)
bool writeFast(const void *buf, uint8_t len)
void enableDynamicPayloads(void)
rf24_datarate_e getDataRate(void)
void writeAckPayload(uint8_t pipe, const void *buf, uint8_t len)
RF24(uint8_t _cepin, uint8_t _cspin)
void setPayloadSize(uint8_t size)
void startFastWrite(const void *buf, uint8_t len, const bool multicast, bool startTx=1)
uint8_t getDynamicPayloadSize(void)
bool setDataRate(rf24_datarate_e speed)
rf24_crclength_e getCRCLength(void)
void openWritingPipe(const uint8_t *address)
void setCRCLength(rf24_crclength_e length)
void whatHappened(bool &tx_ok, bool &tx_fail, bool &rx_ready)
void read(void *buf, uint8_t len)
void openReadingPipe(uint8_t number, const uint8_t *address)
void setPALevel(uint8_t level)
void setAddressWidth(uint8_t a_width)